In a phase-locked loop (PLL), a phase frequency detector compares the phase and frequency of an output signal that is generated by a variable frequency oscillator to the phase and frequency of an input “reference” signal. Based on the comparison, the PLL adjusts the variable frequency oscillator to establish and maintain a constant phase relationship between the output signal and the input signal. Once the phase difference between the two signals becomes substantially constant in time, the PLL is said to be “in lock.”
Often, rather than comparing the phase and frequency of the output signal directly to the phase and frequency of the input signal, a frequency divider is used to first reduce the frequency of the output signal by a division factor to generate a comparison signal. The phase frequency detector then compares the phase and frequency of the comparison signal to the phase and frequency of the input signal and any adjustment needed to the variable frequency oscillator is made based on this comparison.
In a digital PLL (DPLL), the phase frequency detector is often implemented as (or at least includes) a time-to-digital converter (TDC). In general, a TDC is configured to measure the unknown time interval Tint between a rising edge of the comparison signal, generated by the frequency divider of the DPLL, and the next rising edge of the input signal that follows thereafter. The phase difference between the comparison signal and the input signal is, by definition, proportional to this unknown time interval Tint when the frequencies of the two signals are equal.
In at least one implementation of the TDC, the TDC measures the unknown time interval Tint by counting how many intervals of a known reference duration Tr are included in the unknown time interval Tint. FIG. 1 illustrates one such implementation of a TDC 100 referred to as a delay chain TDC. The TDC 100 is used as a phase detector in a DPLL as discussed above and includes delay gates D1-D3 (e.g., buffers or inverters) and flip-flops FF1-FF3. In operation, the comparison signal, produced by the frequency divider of the DPLL in which the TDC 100 is implemented, is successively delayed by the delay gates D1-D3 that each (ideally) has a propagation delay equal to the known reference duration Tr. Upon a rising edge of the input signal being received by the flip-flops F1-F3, the output of each delay gate is sampled and stored in a respective one of the flip-flops FF1-FF3.
The combined output of the flip-flops FF1-FF3 represents a code and this code is fed to an adder as shown in FIG. 1. The number of logical ones in this code corresponds to the number of the delay gates D1-D3 that the rising edge of the comparison signal was able to propagate through before the rising edge of the input signal was received by the flip-flops FF1-FF3. Because the propagation delay of each delay gate D1-D3 is known to be (ideally) equal to the reference duration Tr, counting the number of logical ones in this code using the adder effectively counts the number of intervals of the known reference duration Tr that are included in the unknown time interval Tint. Thus, this count produced by the adder can be used to estimate the unknown time interval Tint and, thereby, the difference in phase between the comparison signal and the input signal.
FIG. 2 provides an example signal waveform 200 that further illustrates the operation of the TDC 100. As can be seen from the signal waveform 200, the comparison signal is successively delayed by the delay gates D1-D3 that each have a propagation delay (ideally) equal to the known reference duration Tr. Upon the rising edge of the input signal being received by the flip-flops F1-F3, the outputs of the delay gates D1-D3 are respectively sampled and stored in the flip-flops F1-F3. The output of the flip-flops F1-F3 after being clocked by the rising edge of the input signal is shown to the right of the signal waveform 200. Based on the number of logical ones in the code represented by the combined output of the flip-flops F1-F3, the TDC 100 measures the unknown time interval Tint between the rising edge of the comparison signal and the rising edge of the input signal. In this instance, the TDC 100 measures the unknown time interval Tint to include, and therefore be equal to, one interval of the known reference duration Tr.
The resolution at which the TDC 100 measures the unknown time interval Tint is generally limited by the propagation delay of the delay gates D1-D3, which are implemented using a buffer or inverter gate for example. In FIG. 2, the measurement of the unknown time interval Tint is off by an amount equal to Tq (referred to as quantization noise) due to the finite delay of the delay gates D1-D3. This quantization noise can increase the phase noise in the output signal generated by the DPLL.
In addition, the limited resolution of the TDC 100 can introduce spurs in the output signal generated by the DPLL when the difference in phase between the input signal and the comparison signal is relatively small, such as when the DPLL is in lock. In many devices, these added spurs are intolerable and/or can cause significant performance issues. For example, in a communication device, such as a cellular phone, the added spurs can prevent the communication device from adequately down-converting and demodulating weak signals that it receives using the output signal generated by the DPLL.
Although the resolution at which the TDC 100 measures the unknown time interval Lint can be increased by reducing the propagation delay of the delay gates in its delay chain, the propagation delay can only be reduced so far due to, for example, power and area constraints for a given process technology.
In addition, although other TDC architectures have been suggested to increase resolution, such as the Vernier TDC and the gated ring oscillator TDC, these architectures generally either fall short of increasing the resolution to acceptable levels for many devices, introduce other sources of noise into the output signal generated by the DPLL, and/or consume too much power.
The embodiments of the present disclosure will be described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.